This invention generally relates to photolithographic patterning of semiconductor features and more particularly to an improved method for manufacturing features such as dual damascene structures while eliminating problems caused by undeveloped photoresist.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased for device features. As one way to overcome such limitations, various methods have been implemented to increase the resolution performance of photoresists and to eliminate interfering effects occurring in the semiconductor wafer manufacturing process.
In the fabrication of semiconductor devices multiple layers may be required for providing a multi-layered interconnect structure. During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as vias, i.e., when the hole extends through an insulating layer between two conductive areas. Electrical interconnecting lines (trench lines) are typically formed over the vias to electrically interconnect the various semiconductor devices within and between multiple layers. The damascene process is a well known semiconductor fabrication method for forming electrical interconnects between layers by forming vias and trench lines.
For example, in the dual damascene process, a via is etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via openings and the trench openings are filled with a metal (e.g., Al, Cu) to form vias and trench lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
In a typical damascene process, for example, a dual damascene manufacturing process known in the art as a via-first-trench last process, conventional photolithographic processes using a photoresist layer is first used to expose and pattern an etching mask on the surface of an etching stop (hard mask) layer overlying the insulating (IMD/ILD) layer, for etching via openings through the insulating layer. Subsequently a similar process is used to define trench openings that are formed substantially over the via openings which in turn define metallic interconnect lines. The via openings and trench openings are subsequently filled with metal to form vias and metal interconnect (trench) lines. The surface may then be planarized by conventional techniques to better define the metal interconnect lines and prepare the substrate for further processing.
One problem with the dual damascene process, especially where vias are adjacent to one another thereby making the distance between metal interconnect lines critical as design rules are scaled down, has been the phenomenon of coherent interference effects forming standing waves in the photoresist due to a reflecting underlayer, e.g., the insulating IMD/ILD layer. Light reflecting from an underlying substrate can lead to size variations in the photoresist pattern making it difficult for critical dimension (CD) control. Efforts to address this problem have included adding dielectric anti-reflectance coating (DARC) layers, for example, silicon oxynitride (SiON), over the insulating layer prior to laying down a photoresist layer, thereby reducing unwanted light reflections.
As an example of a typical dual damascene process, for example, a via-first process, a substrate having a first metallic layer is provided. Next, an insulating layer is formed over the substrate, followed by planarization so that the insulating layer thickness matches the depth of the desired via openings. Thereafter, an hard mask metal nitride layer of, for example, silicon nitride or silicon oxynitride, is formed over the insulating layer which may function as a hard mask in the patterning process to define the via openings. A DARC layer is then deposited over the hard mask layer. Next, a photoresist layer is formed over the DARC layer, which is subsequently patterned for etching via openings and which acts as an etching mask together with the hard mask layer during the etching process. The patterned DARC layer, hard mask layer and insulating layer are then anisotropically etched through a thickness to form via openings through the hard mask layer and insulating layer, with the resulting via openings in closed communication with the underlying conductive layer.
After the via holes are etched, but before the holes are filled with a conductive material, for example, copper, the photoresist mask which remains on top of the desired features may be removed by a dry etching method known as a reactive ion etch (RIE) or ashing process using a plasma formed of O2 or a combination of CF4 and O2 to react with the photoresist material.
As feature sizes in etching process have become increasingly smaller, photolithographic processes have been required to use photoresist activating light (radiation) of smaller wavelength. Typically a deep ultraviolet (DUV) activating light source with wavelength less than about 250, but more typically, from about 193 nm to about 230 nm is used. Exemplary DUV photoresists, for example, include PMMA and polybutene sulfone.
Many processes use a metal nitride as a dielectric anti-reflectance coating (DARC) such as silicon oxynitride (e.g., SION), silicon nitride (e.g., SiN), or titanium nitride (e.g., TiN). Typically, the method of choice for depositing these metal nitride layers is a CVD process where for example, a metal-organic precursor together with nitrogen (and oxygen in the case of SiON) is deposited on a substrate surface, to form a metal nitride. Silicon oxynitride DARC, has been widely used for DUV (deep ultraviolet) lithography because of its tunable refractive index and high etch selectivity to resist.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use or application of metal nitride films such as silicon nitride or silicon oxynitride as hard mask layer or silicon oxynitride as a DARC. For example, nitrogen radicals created due to the presence of nitrogen containing species, such as amines, interfere with chemically amplified resists by neutralizing the acid catalyst, thereby rendering that portion of the photoresist insoluble in the developer. As a result, residual photoresist may remain on patterned feature edges, walls, or floors of features, affecting subsequent etching or metal filling processes thereby degrading electrical property functionality by causing, for example, electrical open circuits or increased resistivity.
Another aspect of advances in semiconductor device processing technology that exacerbates the problem is the increasing use of low-k (low dielectric constant) insulating materials that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials have become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity including interconnecting porosity to allow the achievement of lower dielectric constants. An exemplary low-k material is, for example, carbon doped silicon dioxide (C-oxide) which has a dielectric of about 3 or lower and density of about 1.3 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS). A shortcoming of porous low-k materials is that they readily absorb and provide diffusion pathways through interconnecting pores for chemical species.
As a result, amine and nitrogen-containing species present during the formation of, for example, a SiON hard mask layer or DARC layer, may readily diffuse into adjacent insulating layers, thereby available for interfering with subsequent photoresist processes, such as trench line patterning. The contaminating nitrogen-containing species may diffuse back out of the IMD layer during the photoresist process causing residual exposed but undeveloped photoresist to remain following development, thereby xe2x80x9cpoisoning viasxe2x80x9d by altering remaining deposited on feature edges, sidewalls, and floors. As a result, subsequent metal filling operations of the via openings and trench line openings may result in an open electrical connections or at least increased resistivity in the electrical interconnects.
Another factor which may contribute to the occurrence of undeveloped photoresist remaining on photo-patterned features, for example, dual damascene structures, is related to the ability of the photolithography process to adequately expose the feature patterns. As feature sizes decrease, for example, photolithographic processes have been pushed to their limit. For example, there are well known mathematical relations that predict lithographic imaging behavior, putting constraints on the actual exposure of a given patterned feature due to considerations of depth of focus (DOF) and numerical aperture (NA) of the imaging system. For example, in a dual damascene process the step height of the via may affect subsequent lithographic patterning of an overlying trench line. Decreasing the step height of a via opening would improve exposure conditions of an overlying trench line.
There is therefore a need in the semiconductor processing art to develop a method whereby reliable photolithography processes may be carried out without the detrimental effects of photoresist poisoning caused by undeveloped photoresist remaining on patterned features.
It is therefore an object of the invention to provide a method to develop a method whereby reliable photolithography processes may be carried out without the detrimental effects of photoresist poisoning caused by undeveloped photoresist remaining on patterned features.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for preventing the occurrence of undeveloped photoresist in semiconductor manufacturing processes.
In a first embodiment of the present invention a method is provided for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening extending through a thickness of layers sequentially including a dielectric anti-reflectance layer (DARC), a hard mask layer, and an insulating layer said via opening in closed communication with a conductive region underlying the insulating layer; forming a resinous layer over the DARC layer to include filling the at least one via opening; removing the resinous layer overlying the at least one via opening to form at least one via plug; forming a photoresist layer over the DARC layer for photolithographically patterning a trench line opening disposed substantially over the at least one via opening; photolithographically forming a trench line opening disposed substantially over the at least one via opening to expose a portion of the DARC layer forming a trench line pattern; anisotropically etching according to the trench line pattern through at least a thickness of the DARC layer and hard mask layer to include a portion of the at least one via plug; and anisotropically etching according to the trench line pattern through a portion of a thickness of the insulating layer to form a trench line opening disposed substantially over a remaining portion of the at least one via opening.
In related embodiments the insulating layer has a dielectric constant of less than about 3.0. Further, the insulating layer includes a porous material including interconnecting pores. Further yet, the insulating layer comprises carbon doped oxide.
In other related embodiments, the hard mask layer and DARC layer include a metal nitride. Further, the metal nitride is selected from the group consisting of silicon nitride, silicon oxynitride and titanium nitride. Further yet, the metal nitride is deposited according to a chemical vapor deposition process.
In yet other related embodiments, the resinous layer includes a photoresist resin flowable at room temperature.
In another embodiment, the step of anisotropically etching through a thickness of the DARC layer and hard mask layer to include a portion of the via plug further comprises reactive ion etching (RIE) with an etching chemistry whereby the etching selectivity of the via plug to the hard mask is greater than about 1. Further, the step of anisotropically etching through a thickness of the DARC layer and hard mask layer to include a portion of the via plug further comprises reactive ion etching (RIE) with a nitrogen and oxygen containing plasma having a nitrogen to oxygen ratio of at least about 5.
These and other embodiments, aspects and features of the invention will become better understood from a detailed description of the preferred embodiments of the invention which is described below in conjunction with the accompanying drawings.